As technology nodes continue to evolve, the size of contacts becomes smaller. Self-aligned contact (SAC) processes are required for current mainstream technology nodes and for future smaller-sized nodes. In particular, for logic devices and flash memory devices (e.g., NOR flash memory devices), SAC processes are required with the decreasing size in technology nodes.
FIG. 1A is a cross-sectional view of a contact hole etched in a conventional flash memory device. The flash memory device may include a semiconductor substrate 100 and a gate structure on semiconductor substrate 100. The gate structure may include a gate insulating layer 101, a charge storage layer 103 on gate insulating layer 101, an interlayer dielectric (also referred to as inter-gate dielectric) layer 105 on charge storage layer 103, a gate 107 on interlayer dielectric layer 105, and a hardmask 109 on gate 107. Flash memory device 10 may further include spacers 111 on opposite sides of gate 107 and optionally a mask layer 113 on the gate structure and the substrate. FIG. 1B is an ideal case of etching a contact hole for a contact to an active region in the flash memory device. As shown in FIG. 1A, an interlayer dielectric layer 115 is formed on mask layer 113, or, in other cases, on the gate structure and the substrate. Thereafter, an SAC etching of the contact hole is performed using a patterned mask layer 117 (e.g., photoresist) formed on interlayer dielectric layer 115 extending to the active region (a portion of substrate 100) to form a contact hole 119.
The etch selectivity of the etch process to etch the contact hole is characterized by the ratio of an etch rate of the interlayer dielectric layer (e.g., silicon oxide) relative to the etch rate of the hardmask on the gate (as well as additional sidewalls or sidewall spacers, if any) (e.g., silicon nitride). Ideally, as shown in FIG. 1B, the etch selectivity of the etch process to etch the contact hole is so selected that hardmask 109 remains on gate 107 and spacers 111 remain on sidewalls of gate 107, thereby protecting gate 107.
However, as the size of technology nodes shrinks, the change of the etch selectivity becomes an important consideration for etching. FIGS. 1C and 1D illustrate an example of problems in the flash memory device of FIG. 1A in current SAC processes, particularly, in SAC processes in flash memory devices.
When the etch selectivity of the etch process to etch the contact hole is insufficient, hardmask 109 will be excessively etched and sidewall spacers 111 and/or mask layer 113 will also be consumed, thereby exposing gate 107 causing a short circuit between the gate and the contact in the contact hole, as indicated by the dotted circle in FIG. 1C.
On the other hand, when the etch selectivity of the etch process to etch the contact hole is too high, a portion of interlayer dielectric layer 115 and mask layer 113 (if any) may remain in the contact hole to be formed with resulting risk an open circuit, as shown in FIG. 1D.
For some semiconductor devices, such as flash memory devices (e.g., NOR flash memory devices), due to their high aspect ratio and/or the vias and trenches formed in a single contact hole etch, the above-described problems will become more severe. For logic devices, the problems are similar when SAC processes are used.
Thus, a novel semiconductor device structure and manufacturing method thereof are needed to solve the above-described problems.